The present invention relates to a circuit and method for correcting the duty cycle of a clock signal, the circuit and method including a dead band when the duty cycle of the clock signal is at or close to a 50% duty cycle.
Duty Cycle Correction (DCC) solutions typically use a dual-slope integrator where one phase of the clock charges the integrator positive and the other phase of the clock discharges the integrator. When one dual-slope integrator is used, a comparator compares the integrated voltage to a reference voltage, and mid-point referencing is usually used. With this approach, the comparator outputs a logical “1” or “0” to indicate if the integrated voltage is above or below the reference voltage; a logical “1” or “0” identifies if the duty cycle is above or below the 50%. Adjusting duty cycle using a two-state detector typically results with “dithering” around the desired solution point.
In some cases, two dual-slope integrators have been used (See U.S. Pat. No. 7,570,094 B2). The two integrators are isolated where one integrator directly adjusts the bias on a delay stage to control pull-down slew rate and the other integrator controls the delay stage pull-up slew rate. This is an analog method that directly uses the integrated voltages to bias the delay stage. This method constantly adjusts the bias voltages to acquire a 50% duty cycle from the delay stage(s). In many applications, it is undesirable to constantly chase a clock that jitters or has other small instantaneous variations with the clock duty cycle. This approach does not use a digital solution to correct duty cycle distortion, but generates two analog voltages that are directly applied to the delay stage block to constantly adjust for a 50% output duty cycle.
What is desired, therefore, is an improved duty cycle detector circuit that eliminates the undesirable dithering about the 50% duty cycle operating condition.